A Flexible Logic BIST Scheme and Its Application to SoC Designs
نویسندگان
چکیده
Built-In Self-Test for logic circuits or logic BIST is gaining popularity as an effective solution for the test cost, test quality, and test reuse problems. Logic BIST implements most of ATE functions on chip so that the test cost can be reduced through less test time, less tester memory requirement, or even a cheaper tester. Logic BIST applies a large number of test patterns so that more defects, either modeled or un-modeled, can be detected. In addition, logic BIST makes it easy to conduct the at-speed test for detecting timing-related defects. Furthermore, a BISTed core makes SoC testing easier and such a core can be tested even after being integrated into a system.
منابع مشابه
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects∗ KRISHNA SEKAR AND SUJIT DEY
For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance, reliability and power. Buses and long interconnects being susceptible to crosstalk noise, may lead to functional and timing failures. Existing at-speed interconnect crosstalk test methods propose inserting dedicated interconnect self-test structures in the SoC to ...
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